Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos

 388

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

 SPI_CSR0... 

SPI_CSR3

0xFFFA4030 (0), 0xFFFA8030 (1)

Read/Write

  

Note:

SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the trans-
lated value unless the register is written.

0 = The inactive state value of SPCK is logic level zero. 

1 = The inactive state value of SPCK is logic level one. 

CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.

0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.

1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. 

NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.

0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.

1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select. 

(See the 

.)

The BITS field determines the number of data bits transferred. Reserved values should not be used.

31

30

29

28

27

26

25

24

DLYBCT

23

22

21

20

19

18

17

16

DLYBS

15

14

13

12

11

10

9

8

SCBR

7

6

5

4

3

2

1

0

BITS

CSAAT

–

NCPHA

CPOL

0000

8

0001

9

0010

10

0011

11

0100

12

0101

13

0110

14

0111

15

1000

16