Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos
Los códigos de productos
AT91SAM9M10-G45-EK
469
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
31. Universal Synchronous Asynchronous Receiver Transmitter (USART)
31.1
Description
The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides one full duplex universal syn-
chronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error
detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates
communications with slow remote devices. Multidrop communications are also supported through address bit han-
dling in reception and transmission.
chronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error
detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates
communications with slow remote devices. Multidrop communications are also supported through address bit han-
dling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485, LIN and SPI buses, with ISO7816 T
= 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band
flow control by automatic management of the pins RTS and CTS.
= 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band
flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the trans-
mitter and from the receiver. The PDC provides chained buffer management without any intervention of the
processor.
mitter and from the receiver. The PDC provides chained buffer management without any intervention of the
processor.
31.2
Embedded Characteristics
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo