Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos

 730

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has
already been used and cannot be used again until software has processed the frame and cleared bit zero. In this
case, the DMA block sets the buffer not available bit in the receive status register and triggers an interrupt.

If bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being
received, the frame is discarded and the receive resource error statistics register is incremented.

A receive overrun condition occurs when bus was not granted in time or because HRESP was not OK (bus error).
In a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is
recovered. The next frame received with an address that is recognized reuses the buffer. 

If bit 17 of the network configuration register is set, the FCS of received frames shall not be copied to memory. The
frame length indicated in the receive status field shall be reduced by four bytes in this case.

Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be between 0 and 2047
bytes long, so it is possible to transmit frames longer than the maximum length specified in IEEE Standard 802.3.
Zero length buffers are allowed. The maximum number of buffers permitted for each transmit frame is 128. 

The start location for each transmit buffer is stored in memory in a list of transmit buffer descriptors at a location
pointed to by the transmit buffer queue pointer register. Each list entry consists of two words, the first being the
byte address of the transmit buffer and the second containing the transmit control and status. Frames can be trans-
mitted with or without automatic CRC generation. If CRC is automatically generated, pad is also automatically
generated to take frames to a minimum length of 64 bytes. 

 defines an entry in the transmit

buffer descriptor list. To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte
address to bits 31 to 0 in the first word of each list entry. The second transmit buffer descriptor is initialized with
control information that indicates the length of the buffer, whether or not it is to be transmitted with CRC and
whether the buffer is the last buffer in the frame.

After transmission, the control bits are written back to the second word of the first buffer along with the “used” bit
and other status information. Bit 31 is the “used” bit which must be zero when the control word is read if transmis-
sion is to happen. It is written to one when a frame has been transmitted. Bits 27, 28 and 29 indicate various
transmit error conditions. Bit 30 is the “wrap” bit which can be set for any buffer within a frame. If no wrap bit is
encountered after 1024 descriptors, the queue pointer rolls over to the start in a similar fashion to the receive
queue. 

The transmit buffer queue pointer register must not be written while transmit is active. If a new value is written to
the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue.
If transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to
point to the beginning of the transmit queue. Note that disabling receive does not have the same effect on the
receive queue pointer.

Once the transmit queue is initialized, transmit is activated by writing to bit 9, the 

bit of the network

control register. Transmit is halted when a buffer descriptor with its 

bit set is read, or if a transmit error occurs,

or by writing to the transmit halt bit of the network control register. (Transmission is suspended if a pause frame is
received while the pause enable bit is set in the network configuration register.) Rewriting the start bit while trans-
mission is active is allowed.

Transmission control is implemented with a Tx_go variable which is readable in the transmit status register at bit
location 3. The Tx_go variable is reset when:

– transmit is disabled

– a buffer descriptor with its ownership bit set is read

– a new value is written to the transmit buffer queue pointer register

– bit 10, tx_halt, of the network control register is written