Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The Reset Controller status register (RSTC_SR) provides several status fields:

• RSTTYP field: This field gives the type of the last reset, as explained in previous sections. 

• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software 

reset should be performed until the end of the current one. This bit is automatically cleared at the end of the 
current software reset. 

• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising 

edge. 

• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This 

). If the User Reset is 

disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the 
URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the 
interrupt.

 Reset Controller Status and Interrupt

MCK

NRST

NRSTL

2 cycle 

resynchronization

2 cycle

resynchronization

URSTS

read 

RSTC_SR

Peripheral Access

rstc_irq

if (URSTEN = 0) and

(URSTIEN = 1)