Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos
Los códigos de productos
AT91SAM9M10-G45-EK
790
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Notes:
1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake.
2. Isochronous transfers must use endpoints configured with two or three banks.
An endpoint handles all transactions related to the type of transfer for which it has been configured.
38.5.4
USB V2.0 High Speed BUS Transactions
Each transfer results in one or more transactions over the USB bus.
There are five kinds of transactions flowing across the bus in packets:
1.
Setup Transaction
2.
Data IN Transaction
3.
Data OUT Transaction
4.
Status IN Transaction
5.
Status OUT Transaction
Figure 38-4.
Control Read and Write Sequences
A status IN or OUT transaction is identical to a data IN or OUT transaction.
38.5.5
Endpoint Configuration
The endpoint 0 is always a control endpoint, it must be programmed and active in order to be enabled when the
End Of Reset interrupt occurs.
End Of Reset interrupt occurs.
To configure the endpoints:
• Fill the configuration register (UDPHS_EPTCFG) with the endpoint size, direction (IN or OUT), type (CTRL,
Bulk, IT, ISO) and the number of banks.
• Fill the number of transactions (NB_TRANS) for isochronous endpoints.
Note:
For control endpoints the direction has no effect.
• Verify that the EPT_MAPD flag is set. This flag is set if the endpoint size and the number of banks are correct
compared to the FIFO maximum capacity and the maximum number of allowed banks.
• Configure control flags of the endpoint and enable it in UDPHS_EPTCTLENBx according to
.
Control Write
Setup TX
Data OUT TX
Data OUT TX
Data Stage
Control Read
Setup Stage
Setup Stage
Setup TX
Setup TX
No Data
Control
Control
Data IN TX
Data IN TX
Status Stage
Status Stage
Status IN TX
Status OUT TX
Status IN TX
Data Stage
Setup Stage
Status Stage