Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

USB packets of any length may be transferred when required by the UDPHS Device. These transfers always fea-
ture sequential addressing.

Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance
boost with paged memories. These clock-cycle consuming memory row (or bank) changes will then likely not
occur, or occur only once instead of dozens times, during a single big USB packet DMA transfer in case another
AHB master addresses the memory. This means up to 128-word single-cycle unbroken AHB bursts for Bulk end-
points and 256-word single-cycle unbroken bursts for isochronous endpoints. This maximum burst length is then
controlled by the lowest programmed USB endpoint size (EPT_SIZE bit in the UDPHS_EPTCFGx register) and
DMA Size (BUFF_LENGTH bit in the UDPHS_DMACONTROLx register).

The USB 2.0 device average throughput may be up to nearly 60 MBytes. Its internal slave average access latency
decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. If at least 0 wait-
state word burst capability is also provided by the external DMA AHB bus slaves, each of both DMA AHB busses
need less than 50% bandwidth allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60
MHz.

The UDPHS DMA Channel Transfer Descriptor is described in 

. 

Note: In case of debug, be careful to address the DMA to an SRAM address even if a remap is done.

Example of DMA Chained List: 

Data Buff 1

Data Buff 2

Data Buff 3

Memory Area

Transfer Descriptor

Next Descriptor Address

DMA Channel Address

DMA Channel Control

Transfer Descriptor

Next Descriptor Address

DMA Channel Address

DMA Channel Control

Transfer Descriptor

Next Descriptor Address

DMA Channel Address

DMA Channel Control

UDPHS Registers

(Current Transfer Descriptor)

UDPHS Next Descriptor

DMA Channel Address

DMA Channel Control

Null