Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos
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AT91SAM9M10-G45-EK
851
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
38.6.22
UDPHS DMA Channel Status Register
Name:
UDPHS_DMASTATUSx [x = 1..5]
Addresses:
0xFFF7832C [1], 0xFFF7833C [2], 0xFFF7834C [3], 0xFFF7835C [4], 0xFFF7836C [5]
Access:
Read-write
• CHANN_ENB: Channel Enable Status
0 = if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx
register LDNXT_DSC bit is set.
register LDNXT_DSC bit is set.
When any transfer is ended either due to an elapsed byte count or a UDPHS device initiated transfer end, this bit is auto-
matically reset.
matically reset.
1 = if set, the DMA channel is currently enabled and transfers data upon request.
This bit is normally set or cleared by writing into the UDPHS_DMACONTROLx register CHANN_ENB bit field either by soft-
ware or descriptor loading.
ware or descriptor loading.
If a channel request is currently serviced when the UDPHS_DMACONTROLx register CHANN_ENB bit is cleared, the
DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
• CHANN_ACT: Channel Active Status
0 = the DMA channel is no longer trying to source the packet data.
When a packet transfer is ended this bit is automatically reset.
1 = the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.
When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor
load (if any) and potentially until UDPHS packet transfer completion, if allowed by the new descriptor.
load (if any) and potentially until UDPHS packet transfer completion, if allowed by the new descriptor.
• END_TR_ST: End of Channel Transfer Status
0 = cleared automatically when read by software.
1 = set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer.
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
• END_BF_ST: End of Channel Buffer Status
0 = cleared automatically when read by software.
1 = set by hardware when the BUFF_COUNT downcount reach zero.
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
31
30
29
28
27
26
25
24
BUFF_COUNT
23
22
21
20
19
18
17
16
BUFF_COUNT
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
DESC_LDST
END_BF_ST
END_TR_ST
–
–
CHANN_ACT
CHANN_ENB