Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos
Los códigos de productos
AT91SAM9M10-G45-EK
944
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
The DMAC transfer flow is shown in
.
Figure 41-8.
DMAC Transfer Flow for Source and Destination Linked List Address
41.4.5.4
Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10)
1.
Read the Channel Enable register to choose an available (disabled) channel.
2.
Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt sta-
tus register. Program the following channel registers:
tus register. Program the following channel registers:
Channel enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, DADDRx, CTRLA/Bx, DSCRx
DMAC buffer transfer
Writeback of HDMA_CTRLAx
register in system memory
Is HDMA in
Row1 of
HDMA State Machine Table
Channel Disabled by
hardware
Buffer Complete interrupt
generated here
generated here
HDMA Transfer Complete
interrupt generated here
interrupt generated here
yes
no