Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos

 959

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Note:

1. The addresses for the DMAC registers shown here are for DMA Channel 0. This sequence of registers is repeated succes-

sively for each DMA channel located between 0x064 and 

0x140

.

Register Mapping

0x000

DMAC Global Configuration Register

DMAC_GCFG

Read-write

0x10

0x004

DMAC Enable Register

DMAC_EN

Read-write

0x0

0x008

DMAC Software Single Request Register

DMAC_SREQ

Read-write

0x0

0x00C

DMAC Software Chunk Transfer Request Register

DMAC_CREQ

Read-write

0x0

0x010

DMAC Software Last Transfer Flag Register

DMAC_LAST

Read-write

0x0

0x014

Reserved

–

–

–

0x018

DMAC Error, Chained Buffer transfer completed and Buffer 
transfer completed Interrupt Enable register.

DMAC_EBCIER

Write-only

–

0x01C

DMAC Error, Chained Buffer transfer completed and Buffer 
transfer completed Interrupt Disable register.

DMAC_EBCIDR

Write-only

–

0x020

DMAC Error, Chained Buffer transfer completed and Buffer 
transfer completed Mask Register.

DMAC_EBCIMR

Read-only

0x0

0x024

DMAC Error, Chained Buffer transfer completed and Buffer 
transfer completed Status Register.

DMAC_EBCISR

Read-only

0x0

0x028

DMAC Channel Handler Enable Register

DMAC_CHER

Write-only

–

0x02C

DMAC Channel Handler Disable Register

DMAC_CHDR

Write-only

–

0x030

DMAC Channel Handler Status Register

DMAC_CHSR

Read-only

0x00FF0000

0x034

Reserved

–

–

–

0x038

Reserved

–

–

–

0x03C+ch_num*(0x28)+(0x0)

DMAC Channel Source Address Register

DMAC_SADDR

Read-write

0x0

0x03C+ch_num*(0x28)+(0x4)

DMAC Channel Destination Address Register

DMAC_DADDR

Read-write

0x0

0x03C+ch_num*(0x28)+(0x8)

DMAC Channel Descriptor Address Register

DMAC_DSCR

Read-write

0x0

0x03C+ch_num*(0x28)+(0xC)

DMAC Channel Control A Register

DMAC_CTRLA

Read-write

0x0

0x03C+ch_num*(0x28)+(0x10)

DMAC Channel Control B Register

DMAC_CTRLB

Read-write

0x0

0x03C+ch_num*(0x28)+(0x14)

DMAC Channel Configuration Register

DMAC_CFG

Read-write

0x01000000

0x03C+ch_num*(0x28)+(0x18)

DMAC Channel Source Picture in Picture Configuration 
Register

DMAC_SPIP

Read-write

0x0

0x03C+ch_num*(0x28)+(0x1C)

DMAC Channel Destination Picture in Picture Configuration 
Register

DMAC_DPIP

Read-write

0x0

0x03C+ch_num*(0x28)+(0x20)

Reserved

–

–

–

0x03C+ch_num*(0x28)+(0x24)

Reserved

–

–

–

0x064 - 

0x140

DMAC Channel 1 to 

7

 Register

Read-write

0x0

0x017C- 0x1FC

Reserved

–

–

–