Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Hoja De Datos
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AT91SAM9G25-EK
455
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
Figure 30-23.Deep Power-down Mode Entry
30.5.4.4 Reset Mode
The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-power command bits (LPCB)
to 11 and the clock frozen command bit (CLK_FR) to 1.
to 11 and the clock frozen command bit (CLK_FR) to 1.
When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. Before
enabling this mode, the end user must assume there is not an access in progress.
enabling this mode, the end user must assume there is not an access in progress.
To exit reset mode, the low-power command bits (LPCB) must be set to “00”, clock frozen command bit (CLK_FR) set to
0 and an initialization sequence must be generated by software. See
0 and an initialization sequence must be generated by software. See
30.5.5 Multi-port Functionality
The SDRAM protocol imposes a check of timings prior to performing a read or a write access, thus decreasing the
performance of systems. An access to SDRAM is performed if banks and rows are open (or active). To activate a row in
a particular bank, it has to de-active the last open row and open the new row. Two SDRAM commands must be
performed to open a bank: Precharge and Active command with respect to Trp timing. Before performing a read or write
command, Trcd timing must checked.
performance of systems. An access to SDRAM is performed if banks and rows are open (or active). To activate a row in
a particular bank, it has to de-active the last open row and open the new row. Two SDRAM commands must be
performed to open a bank: Precharge and Active command with respect to Trp timing. Before performing a read or write
command, Trcd timing must checked.
This operation represents a significative loss. (see
NOP READ
BST
NOP
PRCHG
NOP
DEEPOWER
NOP
0
Trp
Enter Deep
Power-down
Mode
Power-down
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
Da
Db
D[15:0]
3
DM[1:0]