Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Hoja De Datos
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AT91SAM9G25-EK
772
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
37.12.5 TWI Clock Waveform Generator Register
Name: TWI_CWGR
Address:
0xF8010010 (0), 0xF8014010 (1), 0xF8018010 (2)
Access: Read-write
Reset:
0x00000000
This register can only be written if the WPEN bit is cleared in the
.
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
CKDIV
15
14
13
12
11
10
9
8
CHDIV
7
6
5
4
3
2
1
0
CLDIV
T
low
CLDIV
(
2
CKDIV
×
(
) 4 )
+
T
MCK
×
=
T
high
CHDIV
(
2
CKDIV
×
(
) 4 )
+
T
MCK
×
=