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ATSAM4S-XPLD
1029
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.4 DACC Channel Disable Register
Name:
DACC_CHDR
Address:
0x4003C014
Access:
Write-only
This register can only be written if the WPEN bit is cleared in
.
• CHx: Channel x Disable
0 = No effect.
1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then re-enabled during a conversion, its
associated analog value and its corresponding EOC flags in DACC_ISR are unpredictable.
associated analog value and its corresponding EOC flags in DACC_ISR are unpredictable.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
CH1
CH0