Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
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ATSAM4S-XPLD
1051
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.3.2.2 Wait Mode
Figure 43-8. Measurement Setup for Wait Mode
VDDIO
= VDDIN = 3.6V
Core clock and master clock stopped
Current measurement as shown in the above figure
BOD disabled
All peripheral clocks deactivated
Table 43-13.
SAM4SD32/SD16/SA16 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with
FAST RC
FAST RC
Sleep Mode
Consumption
Typical value
@25
°C
Core Clock/MCK (MHz)
VDDCORE Consumption
(AMP1)
Total Consumption
(AMP2)
Unit
12
1.1
1.8
mA
8
0.8
1.2
mA
4
0.4
0.7
mA
2
0.3
0.7
mA
1
0.2
0.5
mA
0.5
0.2
0.5
mA
VDDIO
VDDOUT
VDDCORE
VDDIN
Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2