Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 1069

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

2.

The calculated tracking time (t

TRACK

) is higher than 15 t

CP_ADC

.

Set TRANSFER = 1 and TRACTIM = 0.

In this case, a timer will trigger the ADC in order to set the correct sampling rate according to the track time.

The maximum possible sampling frequency will be defined by t

TRACK 

in nanoseconds, computed by the previous formula 

but with minus 15 × t

CP_ADC

 and plus TRANSFER time.



10-bit mode: 1/f

S

 = t

TRACK 

- 15 × t

CP_ADC

 + 5 t

CP_ADC



12-bit mode: 1/f

S

 = t

TRACK 

- 15 × t

CP_ADC

 + 5 t

CP_ADC

Note:

Csample and Ron are taken into account in the formulas.

Note:

1.

Input voltage range can be up to VDDIN without destruction or over-consumption.
If VDDIO < V

ADVREF 

max input voltage is VDDIO.

Input Voltage Range

0

—

V

ADVREF

Input Leakage Current

—

—

±0.5

μA

Input Capacitance

—

—

8

pF