Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 1076

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Notes: 1. 3.3V domain: V

VDDIO 

from 2.85V to 3.6V, maximum external capacitor = 40 pF.

2. 1.8V domain: V

VDDIO 

from 1.65V to 1.95V, maximum external capacitor = 20 pF.

Note that in SPI Master Mode the SAM4S does not sample the data (MISO) on the opposite edge where data clocks out (MOSI) 
but the same edge is used. This is shown in 

The High-speed MultiMedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the
SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.

SPI

0

MISO Setup Time before SPCK Rises (Master)

11.3

—

ns

13.3

—

ns

SPI

1

MISO Hold Time after SPCK Rises (Master)

0

—

ns

0

—

ns

SPI

2

SPCK Rising to MOSI Delay (Master)

-2.0

1.9

ns

-1.9

1.0

ns

SPI

3

MISO Setup Time before SPCK Falls (Master)

16.2

—

ns

18.4

—

ns

SPI

4

MISO Hold Time after SPCK Falls (Master)

0

—

ns

0

—

ns

SPI

5

SPCK Falling to MOSI Delay (Master)

-7

-3.6

ns

-6.7

-4.2

ns

SPI

6

SPCK Falling to MISO Delay (Slave)

3.4

11.1

ns

4.1

13.1

ns

SPI

7

MOSI Setup Time before SPCK Rises (Slave)

0

—

ns

0

—

ns

SPI

8

MOSI Hold Time after SPCK Rises (Slave)

1.3

—

ns

0.9

—

ns

SPI

9

SPCK Rising to MISO Delay (Slave)

3.6

11.5

ns

4.1

12.9

ns

SPI

10

MOSI Setup Time before SPCK Falls (Slave)

0

—

ns

0

—

ns

SPI

11

MOSI Hold Time after SPCK Falls (Slave)

0.8

—

ns

0.9

—

ns

SPI

12

NPCS Setup to SPCK Rising (Slave)

3.3

—

ns

3.5

—

ns

SPI

13

NPCS Hold after SPCK Falling (Slave)

0

—

ns

0

—

ns

SPI

14

NPCS Setup to SPCK Falling (Slave)

4

—

ns

3.6

—

ns

SPI

15

NPCS Hold after SPCK Falling (Slave)

0

—

ns

0

—

ns