Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
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ATSAM4S-XPLD
1085
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.11.7 USART in SPI Mode Timings
Timings are given in the following domain:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF
Figure 43-29.USART SPI Master Mode
Figure 43-30.USART SPI Slave Mode: (Mode 1 or 2)
NSS
SPI
0
MSB
LSB
SPI
1
CPOL=1
CPOL=0
MISO
MOSI
SCK
SPI
5
SPI
2
SPI
3
SPI
4
SPI
4
• the MOSI line is driven by the output pin TXD
• the MISO line drives the input pin RXD
• the SCK line is driven by the output pin SCK
• the NSS line is driven by the output pin RTS
• the MISO line drives the input pin RXD
• the SCK line is driven by the output pin SCK
• the NSS line is driven by the output pin RTS
SCK
MISO
MOSI
SPI
6
SPI
7
SPI
8
NSS
SPI
12
SPI
13
• the MOSI line drives the input pin RXD
• the MISO line is driven by the output pin TXD
• the SCK line drives the input pin SCK
• the NSS line drives the input pin CTS
• the MISO line is driven by the output pin TXD
• the SCK line drives the input pin SCK
• the NSS line drives the input pin CTS