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ATSAM4S-XPLD
1088
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.11.8 Two-wire Serial Interface Characteristics
Notes: 1. Required only for f
TWCK
> 100 kHz.
2. C
B
= capacitance of one bus line in pF. Per I2C Standard, C
b
Max = 400 pF
3.
The TWCK low period is defined as follows:
4.
The TWCK high period is defined as follows:
5. t
CP_MCK
= MCK bus period.
Table 43-56. Two-wire Serial Bus Requirements
Symbol
Parameter
Condition
Min
Max
Units
V
IL
Input Low-voltage
-0.3
0.3 V
VDDIO
V
V
IH
Input High-voltage
0.7xV
VDDIO
V
CC
+ 0.3
V
V
HYS
Hysteresis of Schmitt Trigger Inputs
0.150
—
V
V
OL
Output Low-voltage
3 mA sink current
-
0.4
V
t
R
Rise Time for both TWD and TWCK
20 + 0.1C
300
ns
t
OF
Output Fall Time from V
IHmin
to V
ILmax
10 pF < C
b
< 400 pF
20 + 0.1C
250
ns
C
Capacitance for each I/O Pin
—
10
pF
f
TWCK
TWCK Clock Frequency
0
400
kHz
Rp
Value of Pull-up Resistor
f
TWCK
≤ 100 kHz
f
TWCK
> 100 kHz
t
LOW
Low Period of the TWCK Clock
f
TWCK
≤ 100 kHz
—
µ
s
f
TWCK
> 100 kHz
—
µ
s
t
HIGH
High Period of the TWCK Clock
f
TWCK
≤ 100 kHz
—
µ
s
f
TWCK
> 100 kHz
—
µ
s
t
HD;STA
Hold Time (repeated) START Condition
f
TWCK
≤ 100 kHz
t
HIGH
—
µ
s
f
TWCK
> 100 kHz
t
HIGH
—
µ
s
t
SU;STA
Set-up Time for a Repeated START Condition
f
TWCK
≤ 100 kHz
t
HIGH
—
µ
s
f
TWCK
> 100 kHz
t
HIGH
—
µ
s
t
HD;DAT
Data Hold Time
f
TWCK
≤ 100 kHz
0
3 x T
CP_MCK
µ
s
f
TWCK
> 100 kHz
0
3 x T
CP_MCK
µ
s
t
SU;DAT
Data Setup Time
f
TWCK
≤ 100 kHz
t
LOW -
3 x
t
CP_MCK
—
ns
f
TWCK
> 100 kHz
t
LOW -
3 x
t
CP_MCK
—
ns
t
SU;STO
Setup Time for STOP Condition
f
TWCK
≤ 100 kHz
t
HIGH
—
µ
s
f
TWCK
> 100 kHz
t
HIGH
—
µ
s
t
HD;STA
Hold Time (Repeated) START Condition
f
TWCK
≤ 100 kHz
t
HIGH
—
µ
s
f
TWCK
> 100 kHz
t
HIGH
—
µ
s
V
VDDIO
0,4V
–
3mA
--------------------------------------
1000ns
C
b
-------------------
Ω
V
VDDIO
0,4V
–
3mA
--------------------------------------
300ns
C
b
----------------
Ω
T
low
CLDIV
(
2
CKDIV
×
(
)
4
)
+
T
MCK
×
=
T
high
CHDIV
(
2
CKDIV
×
(
)
4
)
+
T
MCK
×
=