Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 109

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.

Syntax

op{S}{cond} Rd, Rm, Rs

op{S}{cond} Rd, Rm, #n

RRX{S}{cond} Rd, Rm

where:

op

is one of:

ASR Arithmetic Shift Right.

LSL Logical Shift Left.

LSR Logical Shift Right.

ROR Rotate Right.

S

is an optional suffix. If S is specified, the condition code flags are updated on the result  of  the  operation,

see 

.

Rd

is the destination register.

Rm

is the register holding the value to be shifted.

Rs

is the register holding the shift length to apply to the value in Rm. Only the least 

significant byte is used and can be in the range 0 to 255.

n

is the shift length. The range of shift length depends on the instruction:

ASR shift length from 1 to 32

LSL shift length from 0 to 31

LSR shift length from 1 to 32

ROR shift length from 0 to 31

MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.

Operation

ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places specified by
constant n or register Rs.

RRX moves the bits in register Rm to the right by 1. 

In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For details on what
result is generated by the different instructions, see 

Restrictions

Do not use SP and do not use PC.

Condition Flags

If 

S

 is specified:



These instructions update the N and Z flags according to the result



The C flag is updated to the last bit shifted out, except when the shift length is 0, see 

Examples

   ASR    R7, R8, #9  ; Arithmetic shift right by 9 bits

   SLS    R1, R2, #3  ; Logical shift left by 3 bits with flag update

   LSR    R4, R5, #6  ; Logical shift right by 6 bits

   ROR    R4, R5, R6  ; Rotate right by the value in the bottom byte of R6

   RRX    R4, R5      ; Rotate right with extend.