Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 154

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Pack Halfword

Syntax

op{cond} {Rd}, Rn, Rm {, LSL #imm}

op{cond} {Rd}, Rn, Rm {, ASR #imm}

where:

op

is one of:

PKHBT Pack Halfword, bottom and top with shift.

PKHTB Pack Halfword, top and bottom with shift.

cond

Rd

is the destination register.

Rn

is the first operand register

Rm

is the second operand register holding the value to be optionally shifted.

imm

is the shift length. The type of shift length depends on the instruction:
For PKHBT
LSL a left shift with a shift length from 1 to 31, 0 means no shift.
For PKHTB
ASR an arithmetic shift right with a shift length from 1 to 32,
a shift of 32-bits is encoded as 0b00000.

Operation

The PKHBT instruction: 

1.

Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination register.

2.

If shifted, the shifted value of the second operand is written to the top halfword of the destination register.

The PKHTB instruction:

1.

Writes the value of the top halfword of the first operand to the top halfword of the destination register.

2.

If shifted, the shifted value of the second operand is written to the bottom halfword of the destination register.

Restrictions

 must not be SP and must not be PC.

Condition Flags

This instruction does not change the flags.

Examples

PKHBT

R3, R4, R5 LSL #0

; Writes bottom halfword of R4 to bottom halfword of

; R3, writes top halfword of R5, unshifted, to top

; halfword of R3

PKHTB

R4, R0, R2 ASR #1

; Writes R2 shifted right by 1 bit to bottom halfword

; of R4, and writes top halfword of R0 to top

; halfword of R4.