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 171

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following
the ISB are fetched from memory again, after the ISB instruction has been completed.

Condition Flags

This instruction does not change the flags.

Examples

    ISB  ; Instruction Synchronisation Barrier 

Move the contents of a special register to a general-purpose register.

Syntax

MRS{cond} Rd, spec_reg

where:

cond

Rd

is the destination register.

spec_reg

can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

Operation

Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the
Q flag.

In process swap code, the programmers model state of the process being swapped out must be saved, including
relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use
MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence. 

Note:

BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction. 

See 

Restrictions

Rd must not be SP and must not be PC.

Condition Flags

This instruction does not change the flags.

Examples

    MRS  R0, PRIMASK ; Read PRIMASK value and write it to R0 

Move the contents of a general-purpose register into the specified special register.

Syntax

MSR{cond} spec_reg, Rn

where:

cond

Rn

is the source register.

spec_reg

can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

Operation

The register access operation in MSR depends on the privilege level. Unprivileged software can only access the APSR.
See