Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

Los códigos de productos
ATSAM4S-XPLD
Descargar
Página de 1125
 176
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
12.8.2.1 NVIC Programming Hints
The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS provides the
following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
The input parameter IRQn is the IRQ number. For more information about these functions, see the CMSIS
documentation.
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit 
integers, so that:
The array ISER[0] to ISER[1] corresponds to the registers ISER0-ISER1
The array ICER[0] to ICER[1] corresponds to the registers ICER0-ICER1
The array ISPR[0] to ISPR[1] corresponds to the registers ISPR0-ISPR1
The array ICPR[0] to ICPR[1] corresponds to the registers ICPR0-ICPR1
The array IABR[0]to IABR[1] corresponds to the registers IABR0-IABR1
The 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to IP[34] 
corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds the interrupt priority for interrupt n.
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. 
how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that have one
bit per interrupt.
Note:
1.
Each array element corresponds to a single NVIC register, for example the ICER[0] element corresponds to 
the ICER0 register.
Table 12-29. CMSIS Functions for NVIC Control
CMSIS Interrupt Control Function
Description
void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
Set the priority grouping
void NVIC_EnableIRQ(IRQn_t IRQn)
Enable IRQn
void NVIC_DisableIRQ(IRQn_t IRQn)
Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
Return true (IRQ-Number) if IRQn is pending
void NVIC_SetPendingIRQ (IRQn_t IRQn)
Set IRQn pending
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
Clear IRQn pending status
uint32_t NVIC_GetActive (IRQn_t IRQn)
Return the IRQ number of the active interrupt
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
Set priority for IRQn
uint32_t NVIC_GetPriority (IRQn_t IRQn)
Read priority of IRQn
void NVIC_SystemReset (void)
Reset the system
Table 12-30. Mapping of Interrupts to the Interrupt Variables 
Interrupts
Set-enable
Clear-enable
Set-pending
Clear-pending
Active Bit
0-34 ISER[0]
ICER[0]
ISPR[0]
ICPR[0]
IABR[0]
35-63 ISER[1]
ICER[1]
ISPR[1]
ICPR[1]
IABR[1]