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ATSAM4S-XPLD
206
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
12.9.1.15Hard Fault Status Register
Name:
SCB_HFSR
Access: Read-write
Reset: 0x000000000
The HFSR register gives information about events that activate the hard fault handler. This register is read, write to clear. This
means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
• DEBUGEVT: Reserved for Debug Use
When writing to the register, write 0 to this bit, otherwise the behavior is unpredictable.
• FORCED: Forced Hard Fault
It indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because
of priority or because it is disabled:
of priority or because it is disabled:
0: No forced hard fault.
1: Forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault.
• VECTTBL: Bus Fault on a Vector Table
It indicates a bus fault on a vector table read during an exception processing:
0: No bus fault on vector table read.
1: Bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the
exception.
exception.
Note:
The HFSR bits are sticky. This means that, as one or more fault occurs, the associated bits are set to 1. A bit that is
set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
31
30
29
28
27
26
25
24
DEBUGEVT
FORCED
–
23
22
21
20
19
18
17
16
–
15
14
13
12
11
10
9
8
–
7
6
5
4
3
2
1
0
–
VECTTBL
–