Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 222

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

MPU_CTRL

Access: Read-write

Reset: 0x00000800 

The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of the MPU 
when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.

Enables privileged software access to the default memory map:

0: If the MPU is enabled, disables the use of the default memory map. Any memory access to a location not covered by any 
enabled region causes a fault.

1: If the MPU is enabled, enables the use of the default memory map as a background region for privileged software accesses.

When enabled, the background region acts as a region number -1. Any region that is defined and enabled has priority over this 
default map. 

If the MPU is disabled, the processor ignores this bit.

Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers. 

When the MPU is enabled:

0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit.

1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers.

When the MPU is disabled, if this bit is set to 1, the behavior is unpredictable.

Enables the MPU:

0: MPU disabled.

1: MPU enabled.

When ENABLE and PRIVDEFENA are both set to 1:

• For privileged accesses, the default memory map is as described in

. Any access by privileged

software that does not address an enabled memory region behaves as defined by the default memory map.

• Any access by unprivileged software that does not address an enabled memory region causes a memory management

fault.

XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. 

31

30

29

28

27

26

25

24

–

23

22

21

20

19

18

17

16

–

15

14

13

12

11

10

9

8

–

7

6

5

4

3

2

1

0

–

PRIVDEFENA

HFNMIENA

ENABLE