Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

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Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the 
asynchronous output (this can be done automatically by the debugging tool).

IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.

IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high during power-up, and
must be kept in this state during the whole boundary scan operation. The SAMPLE, EXTEST and BYPASS functions are
implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the
processor. This is not IEEE 1149.1 JTAG-compliant.

It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset must be
performed after JTAGSEL is changed.

A Boundary-scan Descriptor Language (BSDL) file is provided on

 Atmel’s web site

 to set up the test.

The Boundary-scan Register (BSR) contains a number of bits which correspond to active pins and associated control
signals.

Each SAM4  input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be
forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the
direction of the pad. 

For more information, please refer to BDSL files available for the SAM4 Series.