Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

A Backup reset occurs when the chip returns from Backup Mode. The core_backup_reset signal is asserted by the
Supply Controller when a Backup reset occurs.

The field RSTTYP in RSTC_SR is updated to report a Backup Reset. 

The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The
NRST input signal is resynchronized with SLCK to insure proper behavior of the system.

The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset
are asserted. 

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The
processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the
value 0x4, indicating a User Reset.

The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as
programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is
driven low externally, the internal reset lines remain asserted until NRST actually rises. 

SLCK

periph_nreset

proc_nreset

NRST

NRST

(nrst_out)

>= EXTERNAL RESET LENGTH

MCK

Processor Startup 

= 2 cycles

Any

Freq.

Resynch.

2 cycles

RSTTYP

Any

XXX

Resynch.

2 cycles

0x4 = User Reset