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ATSAM4S-XPLD
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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
The real-time 32-bit counter can also be supplied by the RTC 1 Hz clock. This mode is interesting when the RTC 1Hz is
calibrated (CORRECTION field of RTC_MR register differs from 0) in order to guaranty the synchronism between RTC
and RTT counters.
calibrated (CORRECTION field of RTC_MR register differs from 0) in order to guaranty the synchronism between RTC
and RTT counters.
Setting the RTC 1HZ clock to 1 in RTT_MR register allows to drive the 32-bit RTT counter with the RTC 1Hz clock. In this
mode, RTTPRESC field has no effect.
mode, RTTPRESC field has no effect.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by
writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the
status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the
interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt
handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear.
writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the
status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the
interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt
handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear.
The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this
value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value
to improve accuracy of the returned value.
value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value
to improve accuracy of the returned value.
The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm
Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its
maximum value, corresponding to 0xFFFF_FFFF, after a reset.
Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its
maximum value, corresponding to 0xFFFF_FFFF, after a reset.
The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a
periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to
32.768 Hz.
periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to
32.768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value.
This also resets the 32-bit counter.
This also resets the 32-bit counter.
When not used, the Real-time Timer can be disabled in order to suppress dynamic power consumption in this module.
This can be achieved by setting the RTTDIS field to 1 in RTT_MR register.
This can be achieved by setting the RTTDIS field to 1 in RTT_MR register.
Figure 15-2. RTT Counting
Prescaler
ALMV
ALMV-1
0
ALMV+1
0
RTPRES - 1
RTT
APB cycle
read RTT_SR
ALMS (RTT_SR)
APB Interface
SCLK
RTTINC (RTT_SR)
ALMV+2
ALMV+3
...
APB cycle