Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 322

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

EEFC_FMR

0x400E0A00 (0), 0x400E0C00 (1)

Read-write

Offset:

0x00

0: Flash Ready does not generate an interrupt.

1: Flash Ready (to accept a new command) generates an interrupt.

This field defines the number of wait states for read and write operations: 

Number of cycles for Read/Write operations = FWS+1

0: The sequential code optimization is enabled.

1: The sequential code optimization is disabled.

No Flash read should be done during change of this register.

0: 128-bit access in read Mode only, to enhance access speed.

1: 64-bit access in read Mode only, to enhance power consumption.

No Flash read should be done during change of this register.

0: The opcode loops optimization is disabled.

1: The opcode loops optimization is enabled.

No Flash read should be done during change of this register.

31

30

29

28

27

26

25

24

–

–

–

–

–

CLOE

–

FAM

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

SCOD

15

14

13

12

11

10

9

8

–

–

–

–

FWS

7

6

5

4

3

2

1

0

–

–

–

–

–

–

FRDY