Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The CRCCU is clocked through the Power Management Controller (PMC), the programmer must first configure the
CRCCU in the PMC to enable the CRCCU clock.

The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU interrupt requires
programming the Interrupt Controller before configuring the CRCCU.

The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured and activated, this CRC
engine performs a checksum computation on a Memory Area. CRC computation is performed from the LSB to MSB bit.
Three different polynomials are available CCITT802.3, CASTAGNOLI and CCITT16, see the bitfield description,

The CRCCU has a DMA controller that supports programmable CRC memory checks. When enabled, the DMA channel
reads a programmable amount of data and computes CRC on the fly.

The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL which need to be mapped in the internal SRAM.
The addresses of these two registers are pointed at by the CRCCU_DSCR register.

TR_ADDR defines the start address of memory area targeted for CRC calculation.

TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the transfer-completed interrupt
enable.

To start the CRCCU, the user needs to set the CRC enable bit (ENABLE) in the CRCCU Mode Register (CRCCU_MR),
then configure it and finally set the DMA enable bit (DMAEN) in the CRCCU DMA Enable Register (CRCCU_DMA_EN). 

When the CRCCU is enabled, the CRCCU reads the predefined amount of data (defined in TR_CTRL) located from
TR_ADDR start address and computes the checksum.

The CRCCU_SR register contains the temporary CRC value.

SRAM 

Memory

CRCCU_DSCR+0x0

---->

TR_ADDR

CRCCU_DSCR+0x4

---->

TR_CTRL

CRCCU_DSCR+0x8

---->

Reserved

CRCCU_DSCR+0xC

---->

Reserved

CRCCU_DSCR+0x10

---->

TR_CRC