Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
Los códigos de productos
ATSAM4S-XPLD
394
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.7.1.1 8-bit NAND Flash
Hardware Configuration
Software Configuration
Perform the following configuration:
Assign the SMC_NFCSx (for example SMC_NFCS3) field in the CCFG_SMCNFCS Register on the Bus Matrix
User Interface.
User Interface.
Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting
to 1 the address bits A21 and A22 during accesses.
to 1 the address bits A21 and A22 during accesses.
NANDOE and NANDWE signals are multiplexed with PIO lines. Thus, the dedicated PIOs must be programmed in
peripheral mode in the PIO controller.
peripheral mode in the PIO controller.
Configure a PIO line as an input to manage the Ready/Busy signal.
Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, the
data bus width and the system bus frequency.
data bus width and the system bus frequency.
In this example, the NAND Flash is not addressed as a “CE don’t care”. To address it as a “CE don’t care”, connect
NCS3 (if SMC_NFCS3 is set) to the NAND Flash CE.
NCS3 (if SMC_NFCS3 is set) to the NAND Flash CE.