Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 507

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be
dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective
optimization of the pins of a product. 

Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. 

Each I/O line of the PIO Controller features:

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An input change interrupt enabling level change detection on any I/O line.

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Additional Interrupt modes enabling rising edge, falling edge, low level or high level detection on any I/O line.

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A glitch filter providing rejection of glitches lower than one-half of PIO clock cycle.

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A debouncing filter providing rejection of unwanted pulses from key or push button operations.

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Multi-drive capability similar to an open drain I/O line.

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Control of the pull-up and pull-down of the I/O line.

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Input visibility and output control.

The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.

An 8-bit parallel capture mode is also available which can be used to interface a CMOS digital image sensor, an ADC, a
DSP synchronous port in synchronous mode, etc...

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Up to 32 Programmable I/O Lines

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Fully Programmable through Set/Clear Registers 

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Multiplexing of Four Peripheral Functions per I/O Line

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For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)

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Input Change Interrupt 

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Programmable Glitch Filter

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Programmable Debouncing Filter

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Multi-drive Option Enables Driving in Open Drain

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Programmable Pull Up on Each I/O Line

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Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time

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Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low Level or High Level

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Lock of the Configuration by the Connected Peripheral

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Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write

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Write Protect Registers

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Programmable Schmitt Trigger Inputs

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Parallel Capture Mode

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Can be used to interface a CMOS digital image sensor, an ADC....

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One Clock, 8-bit Parallel Data and Two Data Enable on I/O Lines

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Data Can be Sampled one time of out two (For Chrominance Sampling Only)

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Supports Connection of one Peripheral DMA Controller Channel (PDC) Which Offers Buffer Reception 
Without Processor Intervention