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ATSAM4S-XPLD
510
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.5
Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is
represented in
represented in
. In this description each signal shown represents but one of up to 32 possible indexes.
Figure 30-3. I/O Line Control Logic
1
0
1
0
1
0
1
0
D
Q
D
Q
DFF
1
0
1
0
11
00
01
10
Programmable
Glitch
or
Debouncing
Filter
PIO_PDSR[0]
PIO_ISR[0]
PIO_IDR[0]
PIO_IMR[0]
PIO_IER[0]
PIO Interrupt
(Up to 32 possible inputs)
PIO_ISR[31]
PIO_IDR[31]
PIO_IMR[31]
PIO_IER[31]
Pad
PIO_PUDR[0]
PIO_PUSR[0]
PIO_PUER[0]
PIO_MDDR[0]
PIO_MDSR[0]
PIO_MDER[0]
PIO_CODR[0]
PIO_ODSR[0]
PIO_SODR[0]
PIO_PDR[0]
PIO_PSR[0]
PIO_PER[0]
PIO_ABCDSR1[0]
PIO_ODR[0]
PIO_OSR[0]
PIO_OER[0]
Resynchronization
Stage
Peripheral A Input
Peripheral D Output Enable
Peripheral A Output Enable
EVENT
DETECTOR
DFF
PIO_IFDR[0]
PIO_IFSR[0]
PIO_IFER[0]
PIO Clock
Clock
Divider
PIO_IFSCSR[0]
PIO_IFSCER[0]
PIO_IFSCDR[0]
PIO_SCDR
Slow Clock
Peripheral B Output Enable
Peripheral C Output Enable
11
00
01
10
Peripheral D Output
Peripheral A Output
Peripheral B Output
Peripheral C Output
PIO_ABCDSR2[0]
Peripheral B Input
Peripheral C Input
Peripheral D Input