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ATSAM4S-XPLD
513
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 30-4. Output Line Timings
30.5.8 Inputs
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of
the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a
peripheral.
the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a
peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels
present on the I/O line at the time the clock was disabled.
present on the I/O line at the time the clock was disabled.
30.5.9 Input Glitch and Debouncing Filters
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the debouncing filter can filter a
pulse of less than 1/2 Period of a Programmable Divided Slow Clock.
pulse of less than 1/2 Period of a Programmable Divided Slow Clock.
The selection between glitch filtering or debounce filtering is done by writing in the registers PIO_IFSCDR (PIO Input
Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter Slow Clock Enable Register). Writing
PIO_IFSCDR and PIO_IFSCER respectively, sets and clears bits in PIO_IFSCSR.
Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter Slow Clock Enable Register). Writing
PIO_IFSCDR and PIO_IFSCER respectively, sets and clears bits in PIO_IFSCSR.
The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter Slow Clock Status
Register).
Register).
If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period of Master Clock.
If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 Period of the
Programmable Divided Slow Clock.
Programmable Divided Slow Clock.
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV field of the PIO_SCDR
(Slow Clock Divider Register)
(Slow Clock Divider Register)
Tdiv_slclk = ((DIV+1)*2).Tslow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 Selected Clock Cycle
(Selected Clock represents MCK or Divided Slow Clock depending on PIO_IFSCDR and PIO_IFSCER programming) is
automatically rejected, while a pulse with a duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is
accepted. For pulse durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may not be
taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1
Selected Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Selected Clock
cycle.
(Selected Clock represents MCK or Divided Slow Clock depending on PIO_IFSCDR and PIO_IFSCER programming) is
automatically rejected, while a pulse with a duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is
accepted. For pulse durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may not be
taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1
Selected Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Selected Clock
cycle.
2 cycles
APB Access
2 cycles
APB Access
MCK
Write PIO_SODR
Write PIO_ODSR at 1
PIO_ODSR
PIO_PDSR
Write PIO_CODR
Write PIO_ODSR at 0