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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The PIO Controller integrates an interface able to read data from a CMOS digital image sensor, a high-speed parallel
ADC, a DSP synchronous port in synchronous mode, etc.... For better understanding and to ease reading, the following
description uses an example with a CMOS digital image sensor.

The CMOS digital image sensor provides a sensor clock, an 8-bit data synchronous with the sensor clock, and two data
enables which are synchronous with the sensor clock too.

As soon as the parallel capture mode is enabled by writing the PCEN bit at 1 in PIO_PCMR (

), the I/O lines connected to the sensor clock (PIODCCLK), the sensor data (PIODC[7:0]) and the sensor data

enable signals (PIODCEN1 and PIODCEN2) are configured automatically as INPUTS. To know which I/O lines are
associated with the sensor clock, the sensor data and the sensor data enable signals, refer to the I/O multiplexing
table(s) in the product datasheet.

Once it is enabled, the parallel capture mode samples the data at rising edge of the sensor clock and resynchronizes it
with the PIO clock domain.

The size of the data which can be read in PIO_PCRHR (

) can be

programmed thanks to the DSIZE field in PIO_PCMR. If this data size is larger than 8 bits, then the parallel capture mode
samples several sensor data to form a concatenated data of size defined by DSIZE. Then this data is stored in
PIO_PCRHR and the flag DRDY is set to 1 in PIO_PCISR (

).

The parallel capture mode can be associated with a reception channel of the Peripheral DMA Controller (PDC). This
enables performing reception transfer from parallel capture mode to a memory buffer without any intervention from the
CPU. Transfer status signals from PDC are available in PIO_PCISR through the flags ENDRX and RXBUFF (see 

).

The parallel capture mode can take into account the sensor data enable signals or not. If the bit ALWYS is set to 0 in
PIO_PCMR, the parallel capture mode samples the sensor data at the rising edge of the sensor clock only if both data
enable signals are active (at 1). If the bit ALWYS is set to 1, the parallel capture mode samples the sensor data at the
rising edge of the sensor clock whichever the data enable signals are.

The parallel capture mode can sample the sensor data only one time out of two. This is particularly useful when the user
wants only to sample the luminance Y of a CMOS digital image sensor which outputs a YUV422 data stream. If the
HALFS bit is set to 0 in PIO_PCMR, the parallel capture mode samples the sensor data in the conditions described
above. If the HALFS bit is set to 1 in PIO_PCMR, the parallel capture mode samples the sensor data in the conditions
described above, but only one time out of two. Depending on the FRSTS bit in PIO_PCMR, the sensor can either sample

PIO Controller

Parallel Capture

Mode

CMOS Digital

Image Sensor

PDC

Data

Status

PIODCCLK

PIODC[7:0]

PIODCEN1

PIODCEN2

PCLK

DATA[7:0]

VSYNC

HSYNC