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 520
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
3.
Write PIO_PCMR to set the PCEN bit to 1 in order to enable the parallel capture mode WITHOUT changing the 
previous configuration.
4.
by waiting the corresponding interrupt.
5.
Check OVRE flag in PIO_PCISR.
6.
Read the data in PIO_PCRHR (
).
7.
.
8.
Write PIO_PCMR to set the PCEN bit to 0 in order to disable the parallel capture mode WITHOUT changing the 
previous configuration.
With PDC
1.
Write PIO_PCIDR and PIO_PCIER (
) in order to configure the parallel capture mode interrupt mask.
2.
Configure PDC transfer in PDC registers.
3.
Write PIO_PCMR (
) to set the fields DSIZE, ALWYS, HALFS and FRSTS in 
order to configure the parallel capture mode WITHOUT enabling the parallel capture mode. 
4.
Write PIO_PCMR to set PCEN bit to 1 in order to enable the parallel capture mode WITHOUT changing the previ-
ous configuration.
5.
Wait for end of transfer by waiting the interrupt corresponding the flag ENDRX in PIO_PCISR (
).
6.
Check OVRE flag in PIO_PCISR.
7.
If a new buffer transfer is expected go to step 
.
8.
Write PIO_PCMR to set the PCEN bit to 0 in order to disable the parallel capture mode WITHOUT changing the 
previous configuration.
30.5.14 Write Protection Registers
To prevent any single software error that may corrupt PIO behavior, certain address spaces can be write-protected by
setting the WPEN bit in the 
 (PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Protect Status Register
(PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the appropriate access key,
WPKEY.
The protected registers are: