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ATSAM4S-XPLD
599
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
32.5
Signal Description
32.6
Product Dependencies
32.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must
first program the PIO controllers to assign the SPI pins to their peripheral functions.
first program the PIO controllers to assign the SPI pins to their peripheral functions.
32.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SPI clock.
PMC to enable the SPI clock.
Table 32-1. Signal Description
Pin Name
Pin Description
Type
Master
Slave
MISO
Master In Slave Out
Input
Output
MOSI
Master Out Slave In
Output
Input
SPCK
Serial Clock
Output
Input
NPCS1-NPCS3
Peripheral Chip Selects
Output
Unused
NPCS0/NSS
Peripheral Chip Select/Slave Select
Output
Input
Table 32-2. I/O Lines
Instance
Signal
I/O Line
Peripheral
SPI
MISO
PA12
A
SPI
MOSI
PA13
A
SPI
NPCS0
PA11
A
SPI
NPCS1
PA9
B
SPI
NPCS1
PA31
A
SPI
NPCS1
PB14
A
SPI
NPCS1
PC4
B
SPI
NPCS2
PA10
B
SPI
NPCS2
PA30
B
SPI
NPCS2
PB2
B
SPI
NPCS3
PA3
B
SPI
NPCS3
PA5
B
SPI
NPCS3
PA22
B
SPI
SPCK
PA14
A