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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt
Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The
processor uses the Handler mode to handle all exceptions except for reset. See 

 and 

 for more information. 

The NVIC registers control interrupt handling. See 

 for more information.

The processor supports the following data types:



32-bit words



16-bit halfwords



8-bit bytes



The processor manages all data memory accesses as little-endian. Instruction memory and Private Peripheral Bus 
(PPB) accesses are always little-endian. See 

For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:



A common way to:



Access peripheral registers



Define exception vectors



The names of:



The registers of the core peripherals



The core exception vectors



A device-independent interface for RTOS kernels, including a debug channel.

The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M4 processor. 

The CMSIS simplifies the software development by enabling the reuse of template code and the combination of CMSIS-
compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include
their peripheral definitions and access functions for those peripherals.

This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions
that address the processor core and the core peripherals.

Note:

This document uses the register short names defined by the CMSIS. In a few cases, these differ from the archi-
tectural short names that might be used in other documents. 

The following sections give more information about the CMSIS:







.