Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 629

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and
one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with
any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot
Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a
slave with sequential or single-byte access. Multiple master capability is supported.

Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost.

A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.

Below, 

 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I

2

C compatible

device.

Note:

1.

START + b000000001 + Ack + Sr



Master, Multi-Master and Slave Mode Operation



Compatibility with Atmel two-wire interface, serial memory and I

2

C compatible devices



One, two or three bytes for slave address



Sequential read/write operations



Bit Rate: Up to 400 kbit/s



General Call Supported in Slave Mode



Connecting to PDC channel capabilities optimizes data transfers in Master Mode only



One channel for the receiver, one channel for the transmitter



Next buffer support

Standard Mode Speed (100 kHz)

Supported

Fast Mode Speed (400 kHz)

Supported

7 or 10 bits Slave Addressing

Supported

START BYTE

Not Supported

Repeated Start (Sr) Condition

Supported

ACK and NACK Management

Supported

Slope control and input filtering (Fast mode)

Not Supported

Clock stretching

Supported

Multi Master Capability

Supported