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ATSAM4S-XPLD
689
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.
Universal Synchronous Asynchronous Receiver Transmitter (USART)
35.1
Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications
with slow remote devices. Multidrop communications are also supported through address bit handling in reception and
transmission.
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications
with slow remote devices. Multidrop communications are also supported through address bit handling in reception and
transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485and SPI buses, with ISO7816 T = 0 or T =
1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an
out-of-band flow control by automatic management of the pins RTS and CTS.
1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an
out-of-band flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter
and from the receiver. The PDC provides chained buffer management without any intervention of the processor.
and from the receiver. The PDC provides chained buffer management without any intervention of the processor.
35.2
Embedded Characteristics
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
Parity generation and error detection
Framing error detection, overrun error detection
MSB- or LSB-first
Optional break generation and detection
By 8 or by-16 over-sampling receiver frequency
Hardware handshaking RTS-CTS
Receiver time-out and transmitter timeguard
Optional Multi-drop Mode with address generation and detection
Optional Manchester Encoding
Full modem line support on USART1 (DCD-DSR-DTR-RI)
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
NACK handling, error counter with repetition and iteration limit
SPI Mode
Master or Slave
Serial Clock programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to MCK/4
IrDA modulation and demodulation
Communication at up to 115.2 Kbps
Test Modes
Remote Loopback, Local Loopback, Automatic Echo