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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e.
respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no
effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization
between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts
looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one
stop bit.
mode.
Figure 35-12.Asynchronous Start Detection 
Figure 35-13.Asynchronous Character Reception
35.7.3.4 Manchester Decoder
When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both
preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use
RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is
detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in
US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP
field in US_MAN. See 
 for available preamble patterns.
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is
set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a
sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If
Sampling
Clock (x16)
RXD
Start
Detection
Sampling
Baud Rate
Clock
RXD
Start
Rejection
Sampling
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
0
1
2
3
4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
D0
Sampling
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Parity
Bit
Stop
Bit
Example: 8-bit, Parity Enabled
Baud Rate
Clock
Start
Detection
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples