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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
the return stack and processor mode. 
return behavior. 
All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence. 
12.4.3.8 Fault Handling
A bus error on:
An instruction fetch or vector table load
A data access
An internally-detected error such as an undefined instruction 
An attempt to execute an instruction from a memory region marked as Non-Executable (XN)
.
A privilege violation or an attempt to access an unmanaged region causing an MPU fault.
Fault Types
 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the
register bit that indicates that the fault has occurred. See 
 for more information about
the fault status registers.
Table 12-10. Exception Return Behavior 
EXC_RETURN[31:0]
Description
0xFFFFFFF1
Return to Handler mode, exception return uses non-floating-point state 
from the MSP and execution uses MSP after return.
0xFFFFFFF9
Return to Thread mode, exception return uses non-floating-point state from 
MSP and execution uses MSP after return.
0xFFFFFFFD
Return to Thread mode, exception return uses non-floating-point state from 
the PSP and execution uses PSP after return.
Table 12-11. Faults 
Fault
Handler
Bit Name
Fault Status Register
Bus error on a vector read
Hard fault
VECTTBL
Fault escalated to a hard fault
FORCED
MPU or default memory map mismatch:
Memory 
management 
fault
-
-
on instruction access
IACCVIOL 
on data access
DACCVIOL
during exception stacking
MSTKERR
during exception unstacking
MUNSKERR
during lazy floating-point state preservation
MLSPERR
Bus error:
Bus fault 
-
-
during exception stacking
STKERR
during exception unstacking
UNSTKERR
during instruction prefetch
IBUSERR
during lazy floating-point state preservation
LSPERR
Precise data bus error
PRECISERR
Imprecise data bus error
IMPRECISERR