Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 754

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

US_MAN

0x40024050 (0), 0x40028050 (1)

Read-write

This register can only be written if the WPEN bit is cleared in 

.

0: The Transmitter Preamble pattern generation is disabled

1 - 15: The Preamble Length is TX_PL x Bit Period

The following values assume that TX_MPOL field is not set:

0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.

1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.

0: The receiver preamble pattern detection is disabled

1 - 15: The detected preamble length is RX_PL x Bit Period

31

30

29

28

27

26

25

24

–

DRIFT

ONE

RX_MPOL

–

–

RX_PP

23

22

21

20

19

18

17

16

–

–

–

–

RX_PL

15

14

13

12

11

10

9

8

–

–

–

TX_MPOL

–

–

TX_PP

7

6

5

4

3

2

1

0

–

–

–

–

TX_PL

00

ALL_ONE

The preamble is composed of ‘1’s

01

ALL_ZERO

The preamble is composed of ‘0’s

10

ZERO_ONE

The preamble is composed of ‘01’s

11

ONE_ZERO

The preamble is composed of ‘10’s