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ATSAM4S-XPLD
781
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.6.14.5Speed Measurement
When SPEEDEN is set in TC_BMR register, the speed measure is enabled on channel 0.
A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in
waveform mode (WAVE bit field set) in TC_CMR2 register. WAVSEL bit field must be defined with 0x10 to clear the
counter by comparison and matching with TC_RC value. ACPC field must be defined at 0x11 to toggle TIOA output.
waveform mode (WAVE bit field set) in TC_CMR2 register. WAVSEL bit field must be defined with 0x10 to clear the
counter by comparison and matching with TC_RC value. ACPC field must be defined at 0x11 to toggle TIOA output.
This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are set.
Channel 0 must be configured in capture mode (WAVE = 0 in TC_CMR0). ABETRG bit field of TC_CMR0 must be
configured at 1 to get TIOA as a trigger for this channel.
configured at 1 to get TIOA as a trigger for this channel.
EDGTRG can be set to 0x01, to clear the counter on a rising edge of the TIOA signal and LDRA field must be set
accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared (LDRB must be set to 0x01). As a
consequence, at the end of each time base period the differentiation required for the speed calculation is performed.
accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared (LDRB must be set to 0x01). As a
consequence, at the end of each time base period the differentiation required for the speed calculation is performed.
The process must be started by configuring the TC_CR register with CLKEN and SWTRG.
The speed can be read on TC_RA0 register in TC_CMR0.
Channel 1 can still be used to count the number of revolutions of the motor.
36.6.15 2-bit Gray Up/Down Counter for Stepper Motor
Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA,TIOB
outputs by means of GCEN bit in TC_SMMRx registers.
outputs by means of GCEN bit in TC_SMMRx registers.
Up or Down count can be defined by writing bit DOWN in TC_SMMRx registers.
It is mandatory to configure the channel in WAVE mode in TC_CMR register.
The period of the counters can be programmed on TC_RCx registers.
Figure 36-20.2-bit Gray Up/Down Counter.
36.6.16 Write Protection System
In order to bring security to the Timer Counter, a write protection system has been implemented.
The write protection mode prevent the write of TC_BMR, TC_FMR, TC_CMRx, TC_SMMRx, TC_RAx, TC_RBx,
TC_RCx registers. When this mode is enabled and one of the protected registers write, the register write request
canceled.
TC_RCx registers. When this mode is enabled and one of the protected registers write, the register write request
canceled.
Due to the nature of the write protection feature, enabling and disabling the write protection mode requires the use of a
security code. Thus when enabling or disabling the write protection mode the WPKEY field of the TC_WPMR register
must be filled with the “TIM” ASCII code (corresponding to 0x54494D) otherwise the register write will be canceled.
security code. Thus when enabling or disabling the write protection mode the WPKEY field of the TC_WPMR register
must be filled with the “TIM” ASCII code (corresponding to 0x54494D) otherwise the register write will be canceled.
TIOAx
TIOBx
DOWNx
TC_RCx
WAVEx = GCENx =1