Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 791

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

TC_SMMRx [x=0..2] 

0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1],

0x40014088 (1)[2]

Read-write 

This register can only be written if the WPEN bit is cleared in 

0 = TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x.

1 = TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter.

0 = Up counter.

1 = Down counter.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

–

7

6

5

4

3

2

1

0

–

DOWN

GCEN