Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 828

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Name: HSMCI_MR

0x40000004

Access: Read-write

This register can only be written if the WPEN bit is cleared in 

.

High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).

High Speed MultiMedia Card Interface clock is divided by 2

(PWSDIV)

 + 1 when entering Power Saving Mode.

Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN bit).

Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data integ-
rity, not bandwidth.

0 = Disables Read Proof.

1 = Enables Read Proof.

Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee data integ-
rity, not bandwidth.

0 = Disables Write Proof.

1 = Enables Write Proof.

Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported.

Warning: BLKLEN value depends on FBYTE.

0 = Disables Force Byte Transfer.

1 = Enables Force Byte Transfer.

0 = 0x00 value is used when padding data in write transfer.

1 = 0xFF value is used when padding data in write transfer.

PADV may be only in manual transfer.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

PDCMODE

PADV

FBYTE

WRPROOF

RDPROOF

PWSDIV

7

6

5

4

3

2

1

0

CLKDIV