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ATSAM4S-XPLD
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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.6.3 PWM Comparison Units
The PWM provides 8
independent comparison units able to compare a programmed value with the current value of the
channel 0 counter (which is the channel counter of all synchronous channels,
).
), to generate software interrupts and to trigger PDC transfer requests for the synchronous channels
(see
Figure 38-14.Comparison Unit Block Diagram
The comparison x matches when it is enabled by the bit CEN in the
(PWM_CMPMx for the comparison x) and when the counter of the channel 0 reaches the comparison value defined by
the field CV in
the field CV in
0 is center aligned (CALG = 1 in
), the bit CVM (in PWM_CMPVx) defines if the
comparison is made when the counter is counting up or counting down (in left alignment mode CALG=0, this bit is
useless).
useless).
If a fault is active on the channel 0, the comparison is disabled and cannot match (see
The user can define the periodicity of the comparison x by the fields CTR and CPR (in PWM_CMPVx). The comparison
is performed periodically once every CPR+1 periods of the counter of the channel 0, when the value of the comparison
period counter CPRCNT (in PWM_CMPMx) reaches the value defined by CTR. CPR is the maximum value of the
comparison period counter CPRCNT. If CPR=CTR=0, the comparison is performed at each period of the counter of the
channel 0.
is performed periodically once every CPR+1 periods of the counter of the channel 0, when the value of the comparison
period counter CPRCNT (in PWM_CMPMx) reaches the value defined by CTR. CPR is the maximum value of the
comparison period counter CPRCNT. If CPR=CTR=0, the comparison is performed at each period of the counter of the
channel 0.
The comparison x configuration can be modified while the channel 0 is enabled by using the
(PWM_CMPVUPDx
registers for the comparison x).
The update of the comparison x configuration and the comparison x value is triggered periodically after the comparison x
update period. It is defined by the field CUPR in the PWM_CMPMx. The comparison unit has an update period counter
independent from the period counter to trigger this update. When the value of the comparison update period counter
CUPRCNT (in PWM_CMPMx) reaches the value defined by CUPR, the update is triggered. The comparison x update
period CUPR itself can be updated while the channel 0 is enabled by using the PWM_CMPMUPDx register.
update period. It is defined by the field CUPR in the PWM_CMPMx. The comparison unit has an update period counter
independent from the period counter to trigger this update. When the value of the comparison update period counter
CUPRCNT (in PWM_CMPMx) reaches the value defined by CUPR, the update is triggered. The comparison x update
period CUPR itself can be updated while the channel 0 is enabled by using the PWM_CMPMUPDx register.
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the
register PWM_CMPMUPDx.
register PWM_CMPMUPDx.
=
fault on channel 0
CNT [PWM_CCNT0]
CNT [PWM_CCNT0]
is decrementing
CALG [PWM_CMR0]
CV [PWM_CMPVx]
=
1
0
1
Comparison x
CVM [PWM_CMPVx]
=
CPRCNT [PWM_CMPMx]
CTR [PWM_CMPMx]
CEN [PWM_CMPM]x