Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 874

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13



Enable of the Interrupts (writing CHIDx and FCHIDx in PWM_IER1 register, and writing WRDYE, ENDTXE, 
TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2 register)



Enable of the PWM channels (writing CHIDx in the PWM_ENA register)

The large number of source clocks can make selection difficult. The relationship between the value in the 

 (PWM_CPRDx) and the 

 (PWM_CDTYx) can help the user in

choosing. The event number written in the Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be
lower than 1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy. 

For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value from between 1 up to 14 in
PWM_CDTYx Register. The resulting duty-cycle quantum cannot be lower than 1/15 of the PWM period.

It is possible to modulate the output waveform duty-cycle, period and dead-times. 

To prevent unexpected output waveform, the user must use the 

, the 

 and the 

PWM_CPRDUPDx and PWM_DTUPDx) to change waveform parameters while the channel is still enabled.



 (PWM_SCM)), 

these registers hold the new period, duty-cycle and dead-times values until the end of the current PWM period and 
update the values for the next period.



If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and UPDM = 0 in 
PWM_SCM register), these registers hold the new period, duty-cycle and dead-times values until the bit 
UPDULOCK is written at “1” (in 

the current PWM period, then update the values for the next period.