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ATSAM4S-XPLD
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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Notes: 1. Some registers are indexed with “ch_num” index ranging from 0 to 3.
0x1AC
PWM Comparison 7 Mode Update Register
PWM_CMPMUPD7
Write-only
0x1B0 - 0x1FC
Reserved
0x200 + ch_num * 
0x20 + 0x00
PWM Channel Mode Register
PWM_CMR
Read-write
0x0
0x200 + ch_num * 
0x20 + 0x04
PWM Channel Duty Cycle Register
PWM_CDTY
Read-write
0x0
0x200 + ch_num * 
0x20 + 0x08
PWM_CDTYUPD
Write-only
0x200 + ch_num * 
0x20 + 0x0C
PWM Channel Period Register
PWM_CPRD
Read-write
0x0
0x200 + ch_num * 
0x20 + 0x10
PWM Channel Period Update Register
PWM_CPRDUPD
Write-only
0x200 + ch_num * 
0x20 + 0x14
PWM_CCNT
Read-only
0x0
0x200 + ch_num * 
0x20 + 0x18
PWM Channel Dead Time Register
PWM_DT
Read-write
0x0
0x200 + ch_num * 
0x20 + 0x1C
PWM Channel Dead Time Update Register
PWM_DTUPD
Write-only
Table 38-6. Register Mapping (Continued)
Offset
Register Name
Access
Reset