Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 890

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

PWM_SCM

0x40020020

Read-write

This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in 

0 = Channel x is not a synchronous channel.

1 = Channel x is a synchronous channel.

Notes: 1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in 

 is set.

2. The update occurs when the Update Period is elapsed.

Selection of the comparison used to set the flag WRDY and the corresponding 

PDC

 transfer request.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

PTRCS

PTRM

–

–

UPDM

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

–

7

6

5

4

3

2

1

0

–

–

–

–

SYNC3

SYNC2

SYNC1

SYNC0

0

MODE0

1

MODE1

Manual write of double buffer registers and automatic update of synchronous channels

2

MODE2

Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous 
channels

3

–

Reserved

0

x

 and the PDC transfer request 

are never set to 1.

1

x

The WRDY flag in 

update period is elapsed, the PDC transfer request is never set to 1.

2

0

 and the PDC transfer request 

are set to 1 as soon as the update period is elapsed.

1

 and the PDC transfer request 

are set to 1 as soon as the selected comparison matches.