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ATSAM4S-XPLD
939
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 39-11.Data OUT Transfer for Ping-pong Endpoint
Note:
An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set.
Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first.
Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1.
This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host.
Once the application comes back to the USB driver, the two flags are set
Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1.
This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host.
Once the application comes back to the USB driver, the two flags are set
.
39.6.2.4 Stall Handshake
A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to
Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)
Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)
A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the
Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.)
Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.)
To abort the current request, a protocol stall is used, but uniquely with control transfer.
The following procedure generates a stall packet:
1.
The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register.
2.
The host receives the stall packet.
3.
The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint
interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt.
interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt.
When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts
due to STALLSENT being set.
due to STALLSENT being set.
Data OUT
PID
ACK
Data OUT 3
Data OUT
Data OUT 2
Data OUT
Data OUT 1
PID
Data OUT 3
Data OUT 1
Data OUT1
Data OUT 2
Data OUT 2
PID
PID
PID
ACK
Cleared by Firmware
USB Bus
Packets
Packets
RX_DATA_BK0 Flag
RX_DATA_BK1 Flag
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 1
Data Payload Written
in FIFO Endpoint Bank 1
FIFO (DPR)
Bank 0
Bank 0
Bank 1
Write by USB Device
Write In Progress
Read By Microcontroller
Read By Microcontroller
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 0
Data Payload Written
in FIFO Endpoint Bank 0
Host Sends First Data Payload
Microcontroller Reads Data 1 in Bank 0,
Host Sends Second Data Payload
Host Sends Second Data Payload
Microcontroller Reads Data2 in Bank 1,
Host Sends Third Data Payload
Host Sends Third Data Payload
Cleared by Firmware
Write by USB Device
FIFO (DPR)
(UDP_CSRx)
(UDP_CSRx)
Interrupt Pending
Interrupt Pending