Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Hoja De Datos
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ATSAMD20-XPRO
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Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
19.5.6 Debug Operation
When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
19.5.7 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
following registers:
z
Interrupt Flag Status and Clear register (INTFLAG - refer to
)
z
Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG - refer to
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to
19.5.8 Analog Connections
Not applicable.
19.6
Functional Description
19.6.1 Principle of Operation
The EIC detects edge or level condition to generate interrupts to the CPU Interrupt Controller or events to the Event
System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by generic clock
GCLK_EIC.
System. Each external interrupt pin (EXTINT) can be filtered using majority vote filtering, clocked by generic clock
GCLK_EIC.
19.6.2 Basic Operation
19.6.2.1 Initialization
The EIC must be initialized in the following order:
1.
Enable CLK_EIC_APB
2.
If edge detection or filtering is required, GCLK_EIC must be enabled
3.
Write the EIC configuration registers (EVCTRL, WAKEUP, CONFIGy)
4.
Enable the EIC
When NMI is used, GCLK_EIC must be enabled after EIC configuration (NMICTRL).
19.6.2.2 Enabling, Disabling and Resetting
The EIC is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The EIC is disabled by
writing a zero to CTRL.ENABLE.
writing a zero to CTRL.ENABLE.
The EIC is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the EIC
will be reset to their initial state, and the EIC will be disabled.
will be reset to their initial state, and the EIC will be disabled.
register for details.
19.6.3 External Pin Processing
Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or
level detection (high or low). The sense of external pins is configured by writing the Interrupt Sense x bits in the Config y
register (CONFIGy.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and
Clear register (INTFLAG) is set when the interrupt condition is met (CONFIGy.SENSEx must be different from zero).
level detection (high or low). The sense of external pins is configured by writing the Interrupt Sense x bits in the Config y
register (CONFIGy.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and
Clear register (INTFLAG) is set when the interrupt condition is met (CONFIGy.SENSEx must be different from zero).